Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 155

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 92. OCD Control Register (OCDCTL)
.
BITS
FIELD
RESET
R/W
PS026308-1207
OCD Status Register
DBGMODE
R/W
7
0
DBGMODE—DEBUG mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and breakpoints are enabled. If the
Flash read protect option bit is enabled, this bit is cleared only by resetting the device. It
cannot be written to 0.
0 = The Z8 Encore! F083A Series device is operating in NORMAL mode
1 = The Z8 Encore! F083A Series device is in DEBUG mode
BRKEN—Breakpoint enable
This bit controls the behavior of the
breakpoints are disabled and the
this bit is 1 when a
is automatically set to 1.
0 = Breakpoints are disabled
1 = Breakpoints are enabled
DBGACK—Debug acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug acknowledge character (
0 = Debug acknowledge is disabled
1 = Debug acknowledge is enabled
Reserved—Must be 0
RST—Reset
Setting this bit to 1 resets the Z8F083A family device. The device goes through a normal
POR sequence with the exception that the On-Chip Debugger is not reset. This bit is
automatically cleared to 0 at the end of reset.
0 = No effect
1 = Reset the Flash read protect option bit device
The OCD status register reports status information about the current state of the debugger
and the system.
BRKEN
R/W
6
0
DBGACK
BRK
R/W
5
0
instruction is decoded, the
FFH
BRK
R
4
0
) to the host when a breakpoint occurs.
BRK
instruction behaves similar to an NOP instruction. If
instruction (Opcode
R
3
0
Reserved
DBGMODE
Z8 Encore!
R
2
0
bit of the OCDCTL register
00H
Product Specification
). By default,
R
1
0
®
On-Chip Debugger
F083A Series
RST
R/W
0
0
143