Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 57

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 17. Port A–D Control Registers (PxCTL)
Table 18. Port A–D Data Direction Sub-Registers (PxDD)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Port A–D Data Direction Subregisters
Port A–D Alternate Function Subregisters
DD7
R/W
R/W
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
7
7
1
PCTL[7:0]—Port Control
The port control register provides access to all subregisters that configure the GPIO port
operation.
The Port A–D data direction subregister is accessed through the Port A–D control register
by writing 01H to the Port A–D address register. See
DD[7:0]—Data direction
These bits control the direction of the associated port pin. Port Alternate function
operation overrides the Data direction register setting.
0 = Output. Data in the Port A–D output data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D input data
register. The output driver is tristated.
The Port A–D alternate function subregister is accessed through the Port A–D control
register by writing
Port A–D alternate function subregisters enable the alternate function selection on pins. If
disabled, the pins functions as GPIO. If enabled, select one of four alternate functions
using alternate function set subregisters 1 and 2 as described in the
Function Set 1 Subregisters
R/W
DD6
R/W
6
6
1
02H
DD5
R/W
R/W
5
5
1
to the Port A–D address register. See
FD1H, FD5H, FD9H, FDDH
on page 48 and
R/W
DD4
R/W
4
4
1
PCTL
00H
Port A–D Alternate Function Set 2
DD3
R/W
R/W
3
3
1
Table
R/W
DD2
R/W
Z8 Encore!
18.
2
2
1
Table 19
General Purpose Input/Output
Product Specification
Port A–D Alternate
DD1
R/W
R/W
on page 46. The
1
1
1
®
F083A Series
R/W
DD0
R/W
0
0
1
45