Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 41

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 10. Stop Mode Recovery Sources and Resulting Action
PS026308-1207
Operating Mode
STOP mode
Caution:
Stop Mode Recovery using Watchdog Timer Time-Out
Stop Mode Recovery using GPIO Port Pin Transition
Stop Mode Recovery Using the External RESET Pin
If the WDT times out during STOP mode, the device undergoes a Stop Mode Recovery
sequence. In the reset status (RSTSTAT) register, the WDT and STOP bits are set to 1. If
the WDT is configured to generate an interrupt upon time-out and the Z8 Encore! F083A
Series device is configured to respond to interrupts, the eZ8 CPU services the WDT
interrupt request following the normal Stop Mode Recovery sequence.
Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. If
any GPIO pin is enabled as a Stop Mode Recovery source, a change in the input pin value
(from high to low or from low to high) initiates Stop Mode Recovery. In the reset status
(RSTSTAT) register, the STOP bit is set to 1.
When the Z8 Encore! F083A Series device is in STOP mode and the external RESET pin
is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin,
the low pulse must be greater than the minimum width specified about 12 ns, or it is
ignored. The EXT bit in the reset status (RSTSTAT) register is set.
In STOP mode, the GPIO port input data registers (PxIN) are disabled. The port input
data registers record the port transition only if the signal stays on the port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the port pin ini-
tiates Stop Mode Recovery without being written to the port input data register or with-
out initiating an interrupt (if enabled for that pin).
Stop Mode Recovery Source
WDT time-out
when configured for Reset
WDT time-out
when configured for interrupt
Data transition on any GPIO port pin
enabled as a Stop Mode Recovery
source
Assertion of external
Debug pin driven Low
RESET
Pin
Action
Stop Mode Recovery
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Stop Mode Recovery
System reset
System reset
Z8 Encore!
Reset and Stop Mode Recovery
Product Specification
®
F083A Series
29