UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 127

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
23.6
23.7
General call address
A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a
Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of
responding to this broadcast message will acknowledge the GC simultaneously and then
behave as a Slave-Receiver. The next byte transmitted by the Master will be accepted and
acknowledged by all Slaves capable of handling the special data bytes. A Slave that cannot
handle one of these data bytes must ignore it by not acknowledging it. The I
lists the possible meanings of the special bytes that follow the first GC address byte, and the
actions to be taken by the Slave device(s) upon receiving them. A common use of the GC by
a Master is to dynamically assign device addresses to Slave devices on the bus capable of a
programmable device address.
The UPSD34xx can generate a GC as a Master-Transmitter, and it can receive a GC as a
Slave. When receiving a GC address (00h), an interrupt will be generated so firmware may
respond to the special GC data bytes if desired.
Serial I/O engine (SIOE)
At the heart of the I
automatically handles low-level I
clock generation and synchronization) and it is controlled and monitored by five SFRs.
The five SFRs shown in
●
●
●
●
●
S1CON - Interface control
S1STA - Interface status
S1DAT - Data shift register
S1ADR - Device address
S1SETUP - Sampling rate
2
C interface is the hardware SIOE, shown in
Figure 42
(Table 78 on page
(Table 82 on page
(Table 75 on page
(Table 84 on page
(Table 80 on page
2
C bus protocol (data shifting, handshaking, arbitration,
are:
130)
132)
129)
133)
132)
Figure
42. The SIOE
2
C specification
I
2
C interface
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