UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 243

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.47
28.5.48
Note:
1
Individual port structures
Ports A, B, C, and D have some differences. The structure of each individual port is
described in the next sections.
Port A structure
Port A supports the following operating modes:
●
●
●
●
●
Port A also supports Open Drain/Slew Rate output drive type options using csiop Drive
Select registers. Pins PA0-PA3 can be configured to fast slew rate, pins PA4-PA7 can be
configured to Open Drain Mode.
See
Figure 84. Port A structure
Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are
capable of Open Drain output option.
From OMC
From AND-
allocator
OR array
From PLD
input bus
Figure 84
MCU I/O Mode
GPLD Output Mode from Output Macrocells MCELLABx
GPLD Input Mode to Input Macrocells IMCAx
Latched Address Output Mode
Peripheral I/O Mode
8032
8032 RD
8032
Data
WR
bits
D bit, periph I/O mode
for details.
PT Output Enable (.OE)
From OMC output (MCELLABx)
PSD module reset
8032
Data
Latched addr bit
bit
registers
D
CSIOP
CLR
D
B
M
U
Q
P
X
Q
Q
Q
1
2
3
5
4
6
registers
One of 6
(MCUI/O)
CSIOP
Direction
Data out
Direction
Drive Select
Control
Data out
(MCUI/O)
Enable Out
Data in (MCUI/O)
Control
Reset
Drive
PSDsoft
Output
select
TO IMCs
1
2
3
4
PERIPH I/O
DATA BIT
M
O
U
P
U
U
X
T
T
MUX
OE
IMCA0 - IMCA7
WR RD
Peripheral I/O
mode sets
direction
PA4 - PA7
1 = open
Enable
Output
output
drain,
Drive type select
Pin
PIO EN
No
hysteresis
PSELx
CMOS
buffer
1 = Fast
Slew rate,
PA0 - PA3
(1)
I/O port A
Pin input
V
logic
DD
V
PSD module
DD
pin, port A
AI09179b
Typical
243/300