UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 229

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.33
Note:
Note:
28.5.34
1
2
1
2
OMC mask registers
There is one OMC Mask register for each of the two groups of eight OMCs shown in
Table 171
individual OMCs. The default value for the mask registers is 00h, which allows loading of all
OMCs. When a given bit in a mask register is set to a '1,' the 8032 is blocked from writing to
the associated OMC flip-flop. For example, suppose that only four of eight OMCs
(MCELLAB0-3) are being used for a state machine. The user may not want the 8032 to write
to all the OMCs in MCELLAB because it would overwrite the state machine registers.
Therefore, the user would want to load the mask register for MCELLAB with the value 0Fh
before writing OMCs.
Table 171. Output macrocell MCELLAB mask register (address = csiop + offset 22h)
Default is 00h after any reset condition
1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Table 172. Output macrocell MCELLBC mask register (address = csiop + offset 23h)
Default is 00h after any reset condition
1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Input macrocells
The GPLD has 20 IMCs, one for each pin on Port A (80-pin device only), one for each pin on
Port B, and for the four pins on Port C that are not JTAG pins. The architecture of one
individual IMC is shown in
they can strobe a signal coming in from a port pin as a latch (gated), or as a register
(clocked), or the IMC can pass the signal without strobing, all prior to driving the signal onto
the PLD input bus. Strobing is useful for sampling and debouncing inputs (keypad inputs,
etc.) before entering the PLD AND-OR arrays. The outputs of IMCs can be read by the 8032
asynchronously when the 8032 reads the csiop registers shown in
and
different methods, one method is by reading IMCs as described here, the other method is
using MCU I/O mode described in a later section.
The optional IMC clocking or gating signal used to strobe pin inputs is driven by a product
term from the AND-OR array. There is one clocking or gating product term available for each
group of four IMCs. Port inputs 0-3 are controlled by one product term and 4-7 by another.
To specify in PSDsoft Express the method in which a signal will be strobed as it enters an
IMC for a given input pin on Port A, B, or C, just specify “PT Clocked register” to use a rising
edge to clock the incoming signal, or specify “PT Clock Latch” to use an active high gate
MCELLAB
MCELLBC
Mask
Mask
Bit 7
Bit 7
Table 175 on page
7
7
and
MCELLAB
MCELLBC
Table
Mask
Mask
Bit 6
Bit 6
6
6
172. The OMC mask registers are used to block loading of data to
230. It is possible to read a PSD module port pin using one of two
MCELLAB
MCELLBC
Mask
Mask
Bit 5
Bit 5
Figure 78 on page
5
5
MCELLAB
MCELLBC
Mask
Mask
Bit 4
Bit 4
4
4
230. IMCs are individually configurable, and
MCELLAB
MCELLBC
Mask
Mask
Bit 3
Bit 3
3
3
MCELLAB
MCELLBC
Mask
Mask
Bit 2
Bit 2
2
2
Table
MCELLAB
MCELLBC
Mask
Mask
Bit 1
Bit 1
173,
1
1
Table
PSD module
MCELLAB
MCELLBC
Mask
Mask
Bit 0
Bit 0
174,
229/300
0
0