UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 189

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
27.13
Table 153. PCASTA register bit definition (continued)
TCM interrupts
There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow
interrupts. The 8 interrupts are “ORed” as one PCA interrupt to the CPU.
By the nature of PCA application, it is unlikely that many of the interrupts occur
simultaneously. If they do, the CPU has to read the interrupt flags and determine which one
to serve. The software has to clear the interrupt flag in the status register after serving the
interrupt.
Table 154. TCMMODE0 - TCMMODE5 (6 registers, reset value 00h)
Table 155. TCMMODE0 - TCMMODE5 register bit definition
EINTF
Bit 7
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
E_COMP
E_COMP 1 - Enable the comparator when set
CAP_PE
CAP_NE
Symbol
Symbol
MATCH
EINTF
INTF4
INTF3
INTF2
INTF1
INTF0
OVF0
Bit 6
TCM4 Interrupt flag
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM3 Interrupt flag
Set by hardware when a match or capture event occurs.
Must be clear with software.
PCA0 Counter OverFlow flag
Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit
EOVFI in PCACON0 is set. OVF1 may be set with either hardware or
software but can only be cleared with software.
TCM2 Interrupt flag
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM1 Interrupt flag
Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM0 Interrupt flag
Set by hardware when a match or capture event occurs.
Must be clear with software.
1 - Enable the interrupt flags (INTF) in the status register to generate an
interrupt.
1 - Enable Capture Mode, a positive edge on the CEXn pin.
1 - Enable Capture Mode, a negative edge on the CEXn pin.
1 - A match from the comparator sets the INTF bits in the status register.
CAP_PE
Bit 5
CAP_NE
Bit 4
Programmable counter array (PCA) with PWM
MATCH
Bit 3
Function
Function
TOGGLE
Bit 2
Bit 1
PWM[1:0]
Bit 0
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