UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 196

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

PSD module
Note:
28.1.15
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Table 158. General I/O pins on PSD module
Four pins on Port C are dedicated to JTAG, leaving four pins for general I/O.
Each I/O pin on the PSD module can be individually configured for different functions on a
pin-by-pin basis
module I/O pins.
●
●
●
●
●
●
JTAG port
In-System Programming (ISP) can be performed through the JTAG signals on Port C. This
serial interface allows programming of the entire PSD module device or subsections of the
PSD module (for example, only Flash memory but not the PLDs) without the participation of
the 8032. A blank UPSD34xx device soldered to a circuit board can be completely
programmed in 10 to 25 seconds. The four basic JTAG signals on Port C; TMS, TCK, TDI,
and TDO form the IEEE-1149.1 interface. The PSD module does not implement the IEEE-
1149.1 Boundary Scan functions, but uses the JTAG interface for ISP an 8032 debug. The
PSD module can reside in a standard JTAG chain with other JTAG devices and it will remain
in BYPASS mode when other devices perform JTAG functions.
ISP programming time can be reduced as much as 30% by using two optional JTAG signals
on Port C, TSTAT and TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to
as “6-pin JTAG”. The FlashLINK JTAG programming cable is available from
STMicroelectronics and PSDsoft Express software is available at no charge from
www.st.com/psm. More JTAG ISP information maybe found in
JTAG debug on page
The MCU module is also included in the JTAG chain within the UPSD34xx device for 8032
debugging and emulation. While debugging, the PSD module is in BYPASS mode.
Conversely, during ISP, the MCU module is in BYPASS mode.
52-pin
80-pin
MCU I/O: 8032 controls the output state of each port pin or it reads input state of each
port pin, by accessing csiop registers at run-time. The direction (in or out) of each pin is
also controlled by csiop registers at run-time.
PLD I/O: PSDsoft Express logic equations and pin configuration selections determine if
pins are connected to OMC outputs or IMC inputs. This is a static and non-volatile
configuration. Port pins connected to PLD outputs can no longer be driven by the 8032
using MCU I/O output mode.
Latched MCU Address Output: Port A or Port B can output de-multiplexed 8032
address signals A0 - A7 on a pin-by-pin basis as specified in csiop registers at run-
time. In addition, Port B can also be configured to output de-multiplexed A8-A15 in
PSDsoft Express.
Data Bus Repeater: Port A can bidirectionally buffer the 8032 data bus (de-
multiplexed) for a specified address range in PSDsoft Express. This is referred to as
Peripheral I/O Mode in this document.
Open Drain Outputs: Some port pins can function as open-drain as specified in csiop
registers at run-time.
Pins on Port D can be used for external chip-select outputs originating from the
DPLD, without consuming OMC resources within the GPLD.
Pkg
(Figure 79 on page
Port A
257.
0
8
Port B
232). Following are the available functions on PSD
8
8
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Port C
4
4
Section 28.6.1: JTAG ISP and
Port D
1
2
Total
13
22