UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 15

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
List of tables
Table 150. PCA1 control register PCACON1 (SFR 0BCh, reset value 00h) . . . . . . . . . . . . . . . . . . . 188
Table 151. PCA1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 152. PCA status register PCASTA (SFR 0A5h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . 188
Table 153. PCASTA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 154. TCMMODE0 - TCMMODE5 (6 registers, reset value 00h). . . . . . . . . . . . . . . . . . . . . . . . 189
Table 155. TCMMODE0 - TCMMODE5 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 156. TCMMODE register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 157. UPSD34xx memory configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 158. General I/O pins on PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 159. HDL statement example generated from PSDsoft express for memory map . . . . . . . . . . 199
Table 160. VM register (address = csiop + offset E2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 161. Data width in different bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 162. CSIOP registers and their offsets (in hexadecimal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 163. Flash memory instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 164. Flash memory status bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 165. Main Flash memory protection register definition (address = csiop + offset C0h) . . . . . . 219
Table 166. Secondary Flash memory protection/security register definition (csiop + offset C2h) . . . 219
Table 167. DPLD and GPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 168. OMC port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 169. Output macrocell MCELLAB (address = csiop + offset 20h) . . . . . . . . . . . . . . . . . . . . . . 228
Table 170. Output macrocell MCELLBC (address = csiop + offset 21h) . . . . . . . . . . . . . . . . . . . . . . 228
Table 171. Output macrocell MCELLAB mask register (address = csiop + offset 22h) . . . . . . . . . . . 229
Table 172. Output macrocell MCELLBC mask register (address = csiop + offset 23h) . . . . . . . . . . . 229
Table 173. Input macrocell port A (address = csiop + offset 0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 174. Input macrocell port B (address = csiop + offset 0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 175. Input macrocell port C (address = csiop + offset 18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 176. Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 177. Port configuration setting requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 178. MCU I/O mode port A data in register (address = csiop + offset 00h) . . . . . . . . . . . . . . . 234
Table 179. MCU I/O mode port B data in register (address = csiop + offset 01h) . . . . . . . . . . . . . . . 234
Table 180. MCU I/O mode port C data in register (address = csiop + offset 10h) . . . . . . . . . . . . . . . 234
Table 181. MCU I/O mode port D Data in register (address = csiop + offset 11h) . . . . . . . . . . . . . . 234
Table 182. MCU I/O mode port A data out register (address = csiop + offset 04h) . . . . . . . . . . . . . . 234
Table 183. MCU I/O mode port B data out register (address = csiop + offset 05h) . . . . . . . . . . . . . . 235
Table 184. MCU I/O mode port C data out register (address = csiop + offset 12h) . . . . . . . . . . . . . . 235
Table 185. MCU I/O mode port D data out register (address = csiop + offset 13h) . . . . . . . . . . . . . . 235
Table 186. MCU I/O mode port A direction register (address = csiop + offset 06h) . . . . . . . . . . . . . . 235
Table 187. MCU I/O mode port B direction in register (address = csiop + offset 07h) . . . . . . . . . . . . 235
Table 188. MCU I/O mode port C direction register (address = csiop + offset 14h) . . . . . . . . . . . . . . 235
Table 189. MCU I/O mode port D direction register (address = csiop + offset 15h) . . . . . . . . . . . . . . 236
Table 190. Latched address output, port A contro register(address = csiop + offset 02h)l . . . . . . . . 238
Table 191. Latched address output, port B contro register (address = csiop + offset 03h)l . . . . . . . . 239
Table 192. Port A pin drive select register (address = csiop + offset 08h) . . . . . . . . . . . . . . . . . . . . 241
Table 193. Port B pin drive select register (address = csiop + offset 09h) . . . . . . . . . . . . . . . . . . . . 242
Table 194. Port C pin drive select register (address = csiop + offset 16h) . . . . . . . . . . . . . . . . . . . . 242
Table 195. Port D pin drive select register (address = csiop + offset 17h) . . . . . . . . . . . . . . . . . . . . 242
Table 196. Port A enable out register (address = csiop + offset 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 197. Port B enable out register (address = csiop + offset 0Dh) . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 198. Port C enable out register (address = csiop + offset 1Ah) . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 199. Port D enable out register (address = csiop + offset 1Bh) . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 200. Power management mode register PMMR0 (address = csiop + offset B0h) . . . . . . . . . . 249
Table 201. Power management mode register PMMR2 (address = csiop + offset B4h) . . . . . . . . . . 249
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