UPSD3422E-40U6 STMicroelectronics, UPSD3422E-40U6 Datasheet - Page 233

• Manufacturer Part Number: UPSD3422E-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4903

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.38
Table 176. Port operating modes (continued)
1. MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.
2. JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions (cannot be
Table 177. Port configuration setting requirements
MCU I/O mode
In MCU I/O mode, the 8032 on the MCU module expands its own I/O by using the I/O Ports
on the PSD module. The 8032 can read PSD module I/O pins, set the direction of the I/O
address output
Latched address output
Peripheral I/O mode
JTAG ISP
programming)
Peripheral I/O
4-PIN JTAG
6-PIN JTAG
Port operating mode
ISP (faster
operating
MCU I/O
used for general I/O).
PLD I/O
Latched
mode
Port
ISP
Choose the MCU I/O
function and declare
the pin name
Choose the PLD
function type, declare
pin name, and specify
logic equation(s)
Choose Latched
Address Out function,
declare pin name
Choose Peripheral I/O
mode function and
specify address range
in DPLD for PSELx
No action required in
PSDsoft to get 4-pin
JTAG. By default TDO,
TDI, TCK, TMS are
dedicated JTAG
functions.
Choose JTAG TSTAT
function for pin PC3
and JTAG TERR
function for pin PC4.
PSDsoft Express to
configure each pin
Required action in
Port A (80-pin
only)
Yes
Yes
No
Logic '0' (default)
N/A
Logic '1'
N/A
N/A
N/A
control register
Value that 8032
writes to csiop
at run-time
Port B
Yes
No
No
Port C
Logic 1 = out of uPSD
Logic 0 = into uPSD
Direction register has
no effect on a pin if
pin is driven from
OMC output
Logic '1' Only
N/A
N/A
N/A
Yes
direction register at
No
No
Value that 8032
writes to csiop
(2)
run-time
Port D
No
No
No
Peripheral I/O mode
JTAG ISP mode on
N/A
N/A
N/A
PIO_EN bit = logic 1
(default is '0')
N/A
N/A
Latched address
VM register at run-
(PIO_EN) of csiop
output mode on
Value that 8032
on page 239
writes to Bit 7
page 238
page 240
Find it
PSD module
time
233/300