MC9S08QD4VSC Freescale Semiconductor, MC9S08QD4VSC Datasheet - Page 38

• Manufacturer Part Number: MC9S08QD4VSC
• Description: IC MCU 4K FLASH 256RAM 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QD4VSC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: S08QD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QD4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• For Use With: DEMO9S08QD4 - BOARD DEMO FOR MC9S08QD FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4 Memory Map and Register Definition
program and erase pulses. An integer number of these timing pulses is used by the command processor to
complete a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
38
1. Write a data value to an address in the flash array. The address and data information from this write
2. Write the command code for the desired command to FCMD. The five valid commands are blank
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
is latched into the flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For page erase commands,
the address can be any address in the 512-byte page of flash to be erased. For mass erase and blank
check commands, the address can be any address in the flash memory. Whole pages of 512 bytes
are the smallest block of flash that can be erased.
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
address and data information).
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
FCLK
Program and Erase Command Execution
1
•
•
Excluding start/end overhead
). The time for one cycle of FCLK is t
Byte program (burst)
A mass or page erase of the last page in flash will erase the factory
programmed internal reference clock trim value.
Do not program any byte in the flash more than once after a successful
erase operation. Reprogramming bits in a byte which is already
programmed is not allowed without first erasing the page in which the
byte resides or mass erasing the entire flash memory. Programming
without first erasing may disturb data stored in the flash.
Byte program
Mass erase
Page erase
Parameter
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Table 4-5. Program and Erase Times
Cycles of FCLK
NOTE
20,000
4000
9
4
FCLK
= 1/f
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
100 ms
20 μs
20 ms
45 μs
1
Freescale Semiconductor