MC9S08QD4VSC Freescale Semiconductor, MC9S08QD4VSC Datasheet - Page 42

• Manufacturer Part Number: MC9S08QD4VSC
• Description: IC MCU 4K FLASH 256RAM 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QD4VSC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: S08QD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QD4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 4
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• For Use With: DEMO9S08QD4 - BOARD DEMO FOR MC9S08QD FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4 Memory Map and Register Definition
4.5.6
The block protection feature prevents the protected region of flash from program or erase changes. Block
protection is controlled through the flash protection register (FPROT). When enabled, block protection
begins at any 512 byte boundary below the last address of flash, 0xFFFF. (see
Protection Register (FPROT and
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the
nonvolatile register block of the flash memory. FPROT cannot be changed directly from application
software so a runaway program cannot alter the block protection settings. Because NVPROT is within the
last 512 bytes of flash, if any amount of memory is protected, NVPROT is itself protected and cannot be
altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands, which allows a way to erase and reprogram a protected flash memory.
The block protection mechanism is illustrated in
last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits
as shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through
0xFFFF), the FPS bits must be set to 1101 111, which results in the value 0xDFFF as the last address of
unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of
NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be
programmed into NVPROT to protect addresses 0xE000 through 0xFFFF.
42
•
•
•
•
•
•
•
•
Writing a second time to a flash address before launching the previous command (There is only
one write to flash for every command.)
Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
Writing to any flash control register other than FCMD after writing to a flash address
Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
Writing any flash control register other than to write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
do blank check and mass erase commands only when the MCU is secure.)
Writing 0 to FCBEF to cancel a partial command
Flash Block Protection
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1
A15
A14
A13
Figure 4-4. Block Protection Mechanism
MC9S08QD4 Series MCU Data Sheet, Rev. 6
NVPROT).”)
A12
A11
Figure
A10
4-4. The FPS bits are used as the upper bits of the
A9
A8
1
A7 A6 A5 A4 A3 A2 A1 A0
1
1
1
Section 4.7.4, “Flash
1
Freescale Semiconductor
1
1
1
1