DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 200

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.3.4
BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select
one of two data buses for break condition A.
Initial value:
Initial value:
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Rev. 3.00 May 17, 2007 Page 142 of 1582
REJ09B0181-0300
Bit
31 to 0 BDA31 to
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9
Bit Name
BDA0
R/W
R/W
Break Data Register A (BDRA) (Only in F-ZTAT Version)
31
15
0
0
bits 15 to 8 and 7 to 0 in BDRA as the break data.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Break Data Bit A
Stores data which specifies a break condition in channel
A.
If the I bus is selected in BBRA, the break data on IDB is
set in BDA31 to BDA0.
If the L bus is selected in BBRA, the break data on LDB
is set in BDA31 to BDA0.
R/W
R/W
25
0
9
0
BDA8
R/W
R/W
24
0
8
0
BDA7
R/W
R/W
23
0
7
0
BDA6
R/W
R/W
22
0
6
0
BDA5
R/W
R/W
21
0
5
0
BDA4
R/W
R/W
20
0
4
0
BDA3
R/W
R/W
19
0
3
0
BDA2
R/W
R/W
18
0
2
0
BDA1
R/W
R/W
17
0
1
0
BDA0
R/W
R/W
16
0
0
0