DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 204

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.3.8
BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select
one of the two data buses for break condition B.
Initial value:
Initial value:
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
Rev. 3.00 May 17, 2007 Page 146 of 1582
REJ09B0181-0300
Bit
31 to 0 BDB31 to
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16
BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9
Bit Name
BDB0
R/W
R/W
Break Data Register B (BDRB) (Only in F-ZTAT Version)
31
15
0
0
bits 15 to 8 and 7 to 0 in BDRB as the break data.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Break Data Bit B
Stores data which specifies a break condition in channel
B.
If the I bus is selected in BBRB, the break data on IDB is
set in BDB31 to BDB0.
If the L bus is selected in BBRB, the break data on LDB
is set in BDB31 to BDB0.
R/W
R/W
25
0
9
0
BDB8
R/W
R/W
24
0
8
0
BDB7
R/W
R/W
23
0
7
0
BDB6
R/W
R/W
22
0
6
0
BDB5
R/W
R/W
21
0
5
0
BDB4
R/W
R/W
20
0
4
0
BDB3
R/W
R/W
19
0
3
0
BDB2
R/W
R/W
18
0
2
0
BDB1
R/W
R/W
17
0
1
0
BDB0
R/W
R/W
16
0
0
0