DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 253
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.5.2
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. Table 8.5 shows the transfer information writeback skip
condition and writeback skipped registers. Note that the CRA and CRB are always written back.
The writeback of the MRA and MRB are always skipped.
Table 8.5
8.5.3
In normal transfer mode, data are transferred in one byte, one word, or one longword units in
response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer
source and destination addresses can be specified as incremented, decremented, or fixed. When the
specified number of transfers ends, an interrupt can be requested to the CPU.
Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in
normal transfer mode.
Table 8.6
Note:
SM1
0
0
1
1
Register
SAR
DAR
CRA
CRB
*
Transfer Information Writeback Skip Function
Normal Transfer Mode
Transfer information writeback is skipped.
Transfer Information Writeback Skip Condition and Writeback Skipped
Registers
Register Function in Normal Transfer Mode
Function
Source address
Destination address
Transfer count A
Transfer count B
DM1
0
1
0
1
SAR
Skipped
Skipped
Written back
Written back
Written Back Value
Not updated
Incremented/decremented/fixed*
Incremented/decremented/fixed*
CRA − 1
Rev. 3.00 May 17, 2007 Page 195 of 1582
Section 8 Data Transfer Controller (DTC)
DAR
Skipped
Written back
Skipped
Written back
REJ09B0181-0300
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