DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 923
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.3.2
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit
7
6
5
4 to 2
Bit Name
FCLRM
SSUMS
SRES
SS Control Register L (SSCRL)
Initial value:
Initial
Value
0
0
0
All 0
R/W:
Bit:
FCLRM SSUMS SRES
R/W
R/W
R/W
R/W
R/W
R
7
0
R/W
6
0
Description
Flag Clear Mode
Selects whether the SSRXI and SSTXI interrupt flags
are cleared on writing to SSTDR or reading from
SSRDR or on completion of DTC transfer. When using
the DTC, set this bit to 0.
0: Flags are cleared when DTC transfer is completed
1: Flags are cleared when the register is accessed
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
5
0
Section 17 Synchronous Serial Communication Unit (SSU)
R
4
0
-
R
3
0
-
Rev. 3.00 May 17, 2007 Page 865 of 1582
R
2
0
-
R/W
1
0
DATS[1:0]
R/W
0
0
REJ09B0181-0300
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