DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 908

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.5
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXIF), receive-error (ERIF),
receive-data-full (RXIF), and break (BRIF).
Table 16.16 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When TXIF request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR)
is set to 1, a TXIF interrupt request is generated.
When RXIF request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXIF
interrupt request is generated. The RXIF interrupt request caused by DR flag is generated only in
asynchronous mode.
When BRIF request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag
in SCLSR is set to 1, a BRIF interrupt request is generated.
When ERIF request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an
ERIF interrupt request is generated.
When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERIF interrupt and BRIF
interrupt without requesting RXIF interrupt.
The TXIF interrupt indicates that transmit data can be written, and the RXIF interrupt indicates
that there is receive data in SCFRDR.
Table 16.16 SCIF Interrupt Sources
Rev. 3.00 May 17, 2007 Page 850 of 1582
REJ09B0181-0300
Interrupt
Source
ERIF
RXIF
BRIF
TXIF
SCIF Interrupt Sources and DTC
Description
Interrupt initiated by receive error (ER)
Interrupt initiated by receive data FIFO full (RDF) or
data ready (DR)
Interrupt initiated by break (BRK) or overrun error
(ORER)
Interrupt initiated by transmit FIFO data empty
(TDFE)
Interrupt
Enable Bit
RIE or REIE
RIE
RIE or REIE
TIE
DTC
Activation
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√

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