ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 117

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Figure 57. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
●
●
In Master mode:
–
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on second clock edge):
–
If CPHA = 0 (data latched on first clock edge):
–
MSBit
GENERATOR
8-bit SHIFT REGISTER
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in
the in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see
collision error (WCOL) on page
CLOCK
SPI
MASTER
LSBit
Figure
Doc ID 12321 Rev 5
59).
MOSI
SCK
SS
MISO
122).
+5V
MISO
MOSI
SCK
SS
MSBit
Not used if SS is managed
by software
8-bit SHIFT REGISTER
SS
On-chip peripherals
, or made free for
SLAVE
Figure
LSBit
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Write
58):