ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 127

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only)
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write collision status (Read-only)
Bit 5 = OVR SPI overrun error (Read-only)
Bit 4 = MODF Mode fault flag (Read-only)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output disable
Bit 1 = SSM SS management
Bit 0 = SSI SS internal mode
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See
(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see
mode fault (MODF) on page
SPICR register. This bit is cleared by a software sequence (An access to the SPICSR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See
page
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
117.
Doc ID 12321 Rev 5
121). An SPI interrupt can be generated if SPIE = 1 in the
Figure
Slave select management on
61).
On-chip peripherals
Overrun condition
Master
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