ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 42

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

Supply, reset and clock management
7.2
Caution:
Caution:
42/247
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain f
of 4 or 8 is selected by 3 option bits. Refer to
the required frequency and the application voltage. Refer to
description.
Table 7.
1. For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.
Figure 14. PLL output frequency timing diagram
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of t
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC
t
Refer to
The PLL is not recommended for applications where timing accuracy is required.
When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock
through the RCCRH and RCCRL registers.
STAB
(see
Target ratio
Section 7.6.5 on page 51
Figure
x4
x4
x8
PLL configurations
(1)
14).
4/8 x
input
freq.
OSC
STARTUP
t
STARTUP
of 4 or 8 MHz. The PLL is enabled and the multiplication factor
Doc ID 12321 Rev 5
2.7 V - 3.65 V
.
3.3 V - 5.5 V
for a description of the LOCKED bit in the SICSR register.
t
LOCK
V
DD
Table 7
LOCKED bit set
PLL
t
STAB
) is reached after a stabilization time of
for the PLL configuration depending on
PLL ratio
Section 15.1
x4
x8
x8
t
ST72344xx ST72345xx
for the option byte
DIV2
OFF
OFF
ON