ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 39
ST72F344K4T6
Manufacturer Part Number
ST72F344K4T6
Description
MCU 8BIT 16KB FLASH MEM 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F344K2T6.pdf
(247 pages)
Specifications of ST72F344K4T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
34
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5611
Available stocks
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Quantity
Price
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Part Number:
ST72F344K4T6
Manufacturer:
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Quantity:
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ST72344xx ST72345xx
6.3.2
Note:
Stack pointer (SP)
Reset value: 01 FFh
The Stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack pointer (called S) can be directly accessed by a LD
instruction.
When the lower limit is exceeded, the Stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure
●
●
A subroutine call occupies two locations and an interrupt five locations in the stack area.
SP7
15
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
On return from interrupt, the SP is incremented and the context is popped from the
stack.
0
7
12.
SP6
0
SP5
0
Doc ID 12321 Rev 5
SP4
0
Read/Write
Read/Write
Figure
12).
SP3
0
SP2
0
Central processing unit
SP1
0
SP0
8
1
0
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