ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 78

MCU 8BIT 16KB FLASH MEM 32-LQFP

ST72F344K4T6

Manufacturer Part Number
ST72F344K4T6
Description
MCU 8BIT 16KB FLASH MEM 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F344K4T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
34
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5611

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I/O ports
10.3
10.4
10.5
78/247
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in
on page 78.
likely to present unwanted side-effects such as spurious interrupt generation.
Figure 36. Interrupt I/O port state transitions
Low-power modes
Table 29.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 30.
Wait
Halt
External interrupt on selected
external event
Mode
Warning:
Interrupt event
Other transitions are potentially risky and should be avoided, since they are
Description
Description of interrupt events
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
floating/pull-up
interrupt
INPUT
01
Doc ID 12321 Rev 5
(reset state)
Event flag
floating
INPUT
00
-
Description
open-drain
OUTPUT
Control bit
10
XX
Enable
DDRx
ORx
= DDR, OR
OUTPUT
push-pull
11
Exit from
ST72344xx ST72345xx
Wait
Yes
Exit from
Figure 36
Halt

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