ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 67

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
1
2
3
4
system is enabled, can generate a Watchdog reset (see
details).
Figure 28. Halt timing overview
Figure 29. Halt mode flowchart
WDGHALT is an option bit. See option byte section for more details.
Peripheral clocked with an external clock source can still be active.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt).
Refer to
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
Table 17: Interrupt mapping on page 59
[MCCSR.OIE=0]
Run
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
instruction
N
WATCHDOG
WDGHALT
(MCCSR.OIE=0)
Halt
Doc ID 12321 Rev 5
RESET
1
INTERRUPT
Halt
Y
1)
256 OR 4096 CPU
ENABLE
3)
256 OR 4096 CPU CLOCK
cycle delay
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
interrupt
Reset
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
or
CYCLE
for more details.
RESET
Y
WATCHDOG
DELAY
vector
Fetch
DISABLE
2)
Section 11.1 on page 82
XX
XX
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
10
Run
4)
4)
Power-saving modes
for more
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