ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 59

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Table 16.
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority up to the next IRET instruction or one of the
previously mentioned instructions.
Table 17.
1. Valid for Halt and Active-halt modes except for the MCC/RTC interrupt source which exits from Active-halt
2. Exit from Halt possible when SPI is in slave mode.
RIM
SIM
TRAP
WFI
No.
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Instruction
mode only and AWU interrupt which exits from AWUFH mode only.
TRAP/ICD Software or ICD interrupt
MCC/RTC RTC time base interrupt
I2C3SNS I2C3SNS address 3 interrupt
I2C3SNS
TIMER A TIMER A peripheral interrupts
TIMER B TIMER B peripheral interrupts
Source
Reset
block
AWU
AVD
SPI
SCI
ei0
ei1
ei2
ei3
I
2
C
Dedicated interrupt instruction set (continued)
Interrupt mapping
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Wait for interrupt
Reset
Auto wakeup interrupt
External interrupt Port PA3, PE1
External interrupt Port PF2:0
External interrupt Port PB3:0
External interrupt Port PB4
I2C3SNS address 1 & 2
interrupt
SPI peripheral interrupts
SCI peripheral interrupt
Auxiliary-voltage-detector
interrupt
I
2
C peripheral interrupt
New description
Description
Doc ID 12321 Rev 5
Load 10 in I1:0 of CC 1
Load 11 in I1:0 of CC 1
Software NMI
Function/example
AWUCSR
I2C3SSR
Register
MCCSR
I2CSRx
SICSR
SPISR
SCISR
TBSR
TASR
label
N/A
N/A
N/A
N/A
N/A
Priority
Highest
Lowest
priority
priority
order
1
1
I1
Exit from
Halt
yes
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
no
H
(2)
(1)
0
1
1
0
I0
FFECh-FFEDh
FFFCh-FFFDh
FFEAh-FFEBh
FFEEh-FFEFh
FFFEh-FFFFh
FFFAh-FFFBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
N
Address
vector
Interrupts
Z
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C