ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 128

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

On-chip peripherals
Note:
128/247
SPI data I/O register (SPIDR)
Reset value: Undefined
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see
Table 55.
7
0021h
0022h
0023h
Address
(Hex.)
D7
Warning:
SPIDR
Reset value
SPICR
Reset value
SPICSR
Reset value
Register
SPI register map and reset values
label
D6
A write to the SPIDR register places data directly into the
shift register for transmission.
Figure
MSB
x
SPIE
0
SPIF
0
7
D5
56).
Doc ID 12321 Rev 5
x
SPE
0
WCOL
0
6
D4
x
SPR2
0
OR
0
Read/Write
5
MODF
MSTR
D3
4
0
0
x
CPOL
3
0
x
x
D2
CPHA
ST72344xx ST72345xx
SOD
2
0
x
x
D1
SPR1
SSM
1
0
x
x
0
SPR0
D0
LSB
SSI
0
x
x
0