M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 140

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
2.04
3.01
REVISION HISTORY
Aug 08, 2007
Feb 02, 2007
Date
27 to 31
Page
81
10
11
12
15
16
17
18
19
23
28
29
31
34
35
37
−
1
2
3
4
7
8
9
t
Table 23
Limits of t
38D5 Group (Flash Memory Version For Development) Datasheet (No.
REJ03B0197) is merged.
Flash memory version contents: added
DESCRIPTION: Description added
Memory size (QzROM version): 640 bytes → 1536 bytes
Power dissipation (Flash memory version): revised
Fig. 1: Flash memory version: “M38D59FFFP” added, Notes: added
Fig. 2: Flash memory version: “M38D59FFHP” added, Notes: added
Table 1: Flash memory version contents: added and separates to Table 2 (Next
Table 3: I/O port P3, I/O port P4: revised
Table 4: OSCSEL → CNV
Fig.4 “Memory type”: Flash memory version added
Memory Type: deleted
Memory size (QzROM version): 640 bytes → 1536 bytes
Fig. 5: Under development products → mass-produced
Table 5: Flash memory version products added
Table 6, Notes on Differences between QzROM and Flash Memory Versions: added
Central Processing Unit: revised
Fig. 8: Flash memory version contents: added
Fig. 9: Flash memory version contents: added
Memory: Flash memory version contents: added
Fig. 10: revised
Fig. 11: revised
Fig. 13: Do not write “1” → Not used (do not write “1”)
Fig. 16 (14) Port P6
INTERRUPTS: revised
• Interrupt Source Selection: interrupt source selection register → interrupt edge
• External Interrupt Pin Selection: INT
Fig. 19: Do not write “1” → Not used (do not write “1”)
<Notes>: Related registers → Related bits, and its explain is revised
Fig. 25: Figure title is revised
• Frequency Divided For Timer: revised
<Notes on Timer 1 to Timer 4>: (2)Writing to Timer 2, Timer 3, Timer 4 → (2)Write
Fig. 28: Figure title is revised
h
(S
CLK2
Notes: revised
Low/X
Timer X output 1 edge switch bit → Timer X output 1 active edge switch bit
P7
Memory size (QzROM version); 640 bytes → 1536 bytes
-R
page)
I/O port; 32 pins → 36 pins
• ROM is revised
• ROM code Protect Address in QzROM version is revised
wH
2
X
D) → t
clock output control bit block is revised
(S
IN
CLK2
mode? → Low-speed/X
h
), t
0
(S
: Revised port Xc switch bit input to low-active
(4/7)
wL
CLK2
(S
SS
38D5 Group Data Sheet
-S
CLK2
/function: revised
selection register
IN2
Description
): t
Timer 2, Timer 3, Timer4
)
port switch bit
c
(S
Summary
0
CLK1
, INT
IN
mode?
)/2–30 → t
1
interrupt switch bit → INT
c
(S
CLK2
)/2–30
0
, INT
1
input