M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 47

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
Fig. 35 Block diagram of UART serial I/O1
Fig. 36 Operation of UART serial I/O1 function
φSOURCE
P4
P4
P4
Transmit or receive clock
2
Transmit buffer register
Receive buffer register
/S
0
1
/R
/T
CLK1
X
X
Serial output TxD
Serial input RxD
D
D
(1)
May 20, 2008 Page 45 of 134
read signal
write signal
BRG count source selection bit
ST detector
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
1/4
2 : As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer when TSC flag = “1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until
Character length selection bit
of the transmit interrupt source selection bit (TIC) of the serial I/O control register.
changing to TSC flag = “0”.
TBE=0
Character length selection bit
TSC=0
TBE=1
7 bits
8 bits
Serial I/O1 synchronous clock selection bit
ST
ST
OE
Address 0018
D
D
0
0
Receive buffer register
PE FE
Receive shift register
Address 001C
ST/SP/PA generator
Address 0018
Frequency division ratio 1/(n+1)
TBE=0
D
D
1
1
Data bus
16
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Note1: φSOURCE indicates the followings:
Data bus
Baud rate generator
Transmit buffer register
Transmit shift register
SP detector
•X
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
16
16
IN
input in the frequency/2, 4, or 8 mode
Serial I/O1 control register
1/16
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock control circuit
RBF=1
SP
SP
TBE=1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Transmit interrupt source selection bit
Serial I/O1 status register
ST
ST
D
0
D
0
Address 001A
RBF=0
1/16
D
D
1
Transmit buffer empty flag (TBE)
1
Transmit shift completion flag (TSC)
∗
UART control register
Transmit interrupt request (TI)
Generated at 2nd bit in 2-stop-bit mode
Address 001B
16
Address 0019
16
16
TSC=1
SP
RBF=1
SP
∗