M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 17

IC 740/38D5 MCU QZ-ROM 80LQFP

M38D59GCHP#U0

Manufacturer Part Number
M38D59GCHP#U0
Description
IC 740/38D5 MCU QZ-ROM 80LQFP
Manufacturer
Renesas Electronics America
Series
740/38000r
Datasheet

Specifications of M38D59GCHP#U0

Core Processor
740
Core Size
8-Bit
Speed
12.5MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, LED, PWM, WDT
Number Of I /o
59
Program Memory Size
48KB (48K x 8)
Program Memory Type
QzROM
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M38D59GCHP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
38D5 Group
Rev.3.04
REJ03B0158-0304
[CPU Mode Register (CPUM)] 003B
The CPU mode register contains the stack page selection bit, etc.
This register is allocated at address 003B
After the system is released from reset, the mode depends on the
OSCSEL pin state in the QzROM version.
When the OSCSEL pin state is GND level, only the on-chip
oscillator starts oscillation. The X
oscillating, and X
operating mode is the on-chip oscillator mode.
When the OSCSEL pin state is Vcc level, the X
oscillation divided by 8 starts oscillation. The on-chip oscillator
stops oscillating, and the X
ports. The operating mode is the frequency/8 mode.
Fig. 8 Structure of CPU mode register
May 20, 2008 Page 15 of 134
CM7
CIN
b7
b7
Notes 1: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2 (bit
and X
CM6
2: In low-speed mode, the X
3: In X
4: 12.5 MHz < f(X
CM5
COUT
CIN
5 of watchdog timer control register (address 0029
even when the on-chip oscillator stop bit is set to “1”.
Also, when the low-speed mode is set, the on-chip oscillator stops regardless of the value of
this bit in the QzROM version. The on-chip oscillator does not stop in the flash memory
version, so set this bit to “1” to stop the oscillation.
In on-chip oscillator mode, even if this bit is set to “1”, the on-chip oscillator does not stop in
the flash memory version, but stops in the QzROM version.
set to “1”.
CM4
IN
and X
pins function as I/O ports. The
mode, the X
CM3
IN
COUT
-X
16
16
CM2
IN
OUT
.
) ≤ 16 MHz is not available in the frequency/2 mode.
pins function as I/O
IN
CM1
-X
oscillation stops
OUT
CM8
CIN
CM0
b0
b0
oscillation does not stop even if the X
-X
IN
COUT
CPU mode register 2
CPUM2
(address 0011
(
(
CPU mode register
CPUM
(address 003B
(
(
-X
Processor mode bits
Stack page selection bit
Internal system clock selection bit
Port Xc switch bit
X
Main clock division ratio selection bit
(Valid only when CM3=0)
OUT
On-chip oscillator stop bit
Not used (do not write “1”)
Not used (returns “0” when read)
Not used (do not write “1”)
IN
oscillation stops if the port X
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
0 : 0 page
1 : 1 page
0 : Main clock selected
1 : X
0 : I/O port function (Oscillation stop)
1 : X
0 : Oscillating
1 : Stopped
b7 b6
0 0 : f(X
0 1 : f(X
1 0 : f(X
1 1 : On-chip oscillator
–X
0 : Oscillating
1 : Stopped
(includes OCO, X
OUT
CIN
CIN
In the flash memory version, only the on-chip oscillator starts
oscillating. The X
X
is the on-chip oscillator mode.
When the main clock or sub-clock is used, after the X
oscillation and the X
the on-chip oscillator mode etc. until the oscillation stabilizes,
and then switch the operation mode.
When the main clock is not used (X
external clock input are not used), connect the X
through a resistor and leave X
[CPU Mode Register 2 (CPUM2)] 0011
The CPU mode register 2 contains the control bits for the on-chip
oscillator.
The CPU mode register 2 is allocated at address 0011
16
Not available
oscillation stop bit
–X
–X
16
IN
IN
IN
CIN
, QzROM version, OSCSEL=L, initial value: 00
, QzROM version, OSCSEL=L, initial value: E0
)/2 (frequency/2 mode)
)/8 (frequency/8 mode)
)/4 (frequency/4 mode)
COUT
COUT
QzROM version, OSCSEL=H, initial value: 01
Flash memory version,
QzROM version, OSCSEL=H, initial value: 40
Flash memory version,
16
and X
)), the on-chip oscillator does not stop
(2)
selected
oscillating function
COUT
IN
(4)
)
(1)
(3)
pins function as I/O ports. The operating mode
IN
C
IN
-X
switch bit is set to “0”.
-X
CIN
OUT
OUT
-X
oscillation stop bit is
COUT
oscillation stops oscillating, and the
OUT
initial value: 00
initial value: E0
oscillation are enabled, wait in
open.
IN
-X
OUT
16
16
16
16
16
16
16
)
)
)
oscillation and an
)
)
)
IN
16
pin to V
.
IN
-X
OUT
CC

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