M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 54

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
LCD DRIVE CONTROL CIRCUIT
The 38D5 Group has the built-in Liquid Crystal Display (LCD)
drive control circuit consisting of the following.
• LCD display RAM
• Segment output disable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit
A maximum of 36 segment output pins and 8 common output
pins can be used.
Up to 256 pixels can be controlled for an LCD display. When the
LCD enable bit is set to “1” after data is set in the LCD mode
register, the segment output disable register, and the LCD display
RAM, the LCD drive control circuit starts reading the display
data automatically, performs the bias control and the duty ratio
control, and displays the data on the LCD panel.
Fig. 43 Structure of LCD related registers
b7
b7
b7
May 20, 2008 Page 52 of 134
b0
b0
b0
LCD mode register 1
(LM 1 : address 0013
Segment output disable register 0
(SEG0 : address 0FF4
Segment output disable register 2
(SEG2 : address 0FF6
Segment output disable bit 0
Segment output disable bit 1
Segment output disable bit 2
Segment output disable bit 3
Segment output disable bit 4
Segment output disable bit 5
Segment output disable bit 6
Segment output disable bit 7
Segment output disable bit 16
Segment output disable bit 17
Segment output disable bit 18
Segment output disable bit 19
Not used (do not write “1”)
Duty ratio selection bits
b2b1b0
Bias control bit
LCD enable bit
LCD circuit divider division ratio selection bits
b6b5
LCDCK count source selection bit
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P0
0 : Segment output SEG
1 : Output port P1
0 : Segment output SEG
1 : Output port P1
0 : Segment output SEG
1 : Output port P3
0 : Segment output SEG
1 : Output port P3
0 0 0 : 1 (Static)
0 0 1 : 2 (use COM
0 1 0 : 3 (use COM
0 1 1 : 4 (use COM
1 0 0 to 1 1 0 : Not available
1 1 1 : 8 (COM
0 : 1/3 bias
1 : 1/2 bias
0 : LCD OFF
1 : LCD ON
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
0 : f(X
1 : φSOURCE/8192
CIN
)/32
(1)
0
-COM
0
1
2
3
4
5
6
7
0-
4-
0-
4-
16
16
16
P1
P1
P3
P3
0
0
0
)
, COM
-COM
-COM
)
)
3
7
3
7
(3)
(3)
7
)
8
9
10
11
12
13
14
15
16-
20-
24-
28-
2
3
SEG
SEG
SEG
SEG
1
)
)
)
19
23
27
31
(2)
Notes 1: When “1” is selected as duty ratio by the duty ratio selection bits,
2: LCDCK is a clock for the LCD timing controller.
3: Only pins set to output ports by the direction register can be controlled
4: When disabling the voltage multiplier circuit, the C
φSOURCE indicates the followings:
set “1” to the bias control bit.
to switch to output ports or segment outputs by the segment output
disable register.
function as input ports P7
b7
b7
•X
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
IN
.
Table 12
input in the frequency/2, 4, or 8 mode
Duty ratio
1
2
3
4
8
Maximum number of display pixels at each duty ratio
0
/INT
01
, P7
b0
b0
36 dots
or 8 segment LCD 4 digits
72 dots
or 8 segment LCD 9 digits
108 dots
or 8 segment LCD 13 digits
144 dots
or 8 segment LCD 18 digits
256 dots
or 8 segment LCD 32 digits
1
/INT
Maximum number of display pixels
LCD mode register 2
(LM2 : address 0014
Segment output disable register 1
(SEG1 : address 0FF5
Voltage multiplier circuit control bit
V
Not used (returns “0” when read)
Segment output disable bit 8
Segment output disable bit 9
Segment output disable bit 10
Segment output disable bit 11
Segment output disable bit 12
Segment output disable bit 13
Segment output disable bit 14
Segment output disable bit 15
0 : Voltage multiplier circuit disabled
1 : Voltage multiplier circuit enabled (C
0 : Connect LCD internal V
1 : Connect LCD internal V
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
0 : Segment output SEG
1 : Output port P2
L3
11
connection bit
.
(Input ports P7
1
and C
2
0
0
1
2
3
4
5
6
7
16
pins
/INT
)
16
(4)
)
(3)
01
0
1
2
3
4
5
6
7
, P7
L3
L3 to
1
to V
/INT
V
L3
CC
11
pin
)
1
, C
2
pins)