DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 14

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Rev. 3.00 Mar 21, 2006 page xii of liv
Item
14.4.2 Interval Timer
Mode
Figure 14.4 OVF Flag
Set Timing
14.6.2 Conflict
between Timer
Counter (TCNT) Write
and Increment
Figure 14.7 Conflict
between TCNT Write
and Increment
15.1 Features
Figure 15.1 Block
Diagram of SCI
16.3.5 I
Control Register
(ICCR)
2
C Bus
Page
354
357
360
424
Revision (See Manual for Details)
Figure 14.4 amended
TCNT
Overflow signal
(internal signal)
OVF
Figure 14.7 amended
Figure legend amended
(Before) SCMR: Smart card mode register
Serial interface mode register
Table amended
Bit
5
4
Address
Internal write signal
Bit Name
MST
TRS
Initial Value R/W
0
0
R/W
R/W
H'FF
TCNT write cycle
Description
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
format. In slave receive mode with I
R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit mode
automatically by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
T
1
T
2
(After) SCMR:
H'00
2
C bus format, the
2
C bus