DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 626

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Section 19 Host Interface LPC Interface (LPC)
The scope of the initialization in each mode is shown in table 19.6.
Table 19.6 Scope of Initialization in Each Host Interface Mode
Items Initialized
LPC transfer cycle sequencer (internal state),
LPCBSY and ABRT flags
SERIRQ transfer cycle sequencer (internal state),
CLKREQ and IRQBSY flags
Host interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1 to C/D3, OBF1, OBF2,
OBF3A, OBF3B, SWMF, DBU), GA20 (internal state)
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2,
IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to
IRQ11E3), Q/C flag, SELREQ bit
LRST flag
SDWN flag
LRSTB bit
SDWNB bit
SDWNE bit
Host interface operation control bits
(LPC3E to LPC1E, FGA20E, LADR3, IBFIE1 to IBFIE3, PMEE,
PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3,
SELIRQ1, SELSMI, SELIRQ6, SELIRQ9 to SELIRQ12)
LRESET signal
LPCPD signal
LAD3 to LAD0, LFRAME, LCLK, SERIRQ,
CLKRUN signals
PME, LSMI, LSCI, GA20 signals (when function
is selected)
PME, LSMI, LSCI, GA20 signals (when function
is not selected)
Note: System reset: Reset by STBY input, RES input, or WDT overflow
Rev. 3.00 Mar 21, 2006 page 570 of 788
REJ09B0300-0300
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
System
Reset
Initialized
Initialized
Initialized
Initialized
Initialized
(0)
Initialized
(0)
Initialized
(0)
Initialized
(0)
Initialized
(0)
Initialized
Input (port
function
LPC Reset
Initialized
Initialized
Initialized
Initialized
Can be
set/cleared
Initialized
(0)
HR: 0
SR: 1
Initialized
(0)
Initialized
(0)
Retained
Input
Input
Input
Output
Port function
LPC
Shutdown
Initialized
Initialized
Retained
Retained
Can be
set/cleared
Can be
set/cleared
0 (can be set)
HS: 0
SS: 1
HS: 1
SS: 0 or 1
Retained
Input
Input
Hi-Z
Hi-Z
Port function