DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 533

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Table 16.10 Permissible SCL Rise Time (t
6. The I
IICX
0
1
and 300 ns. The I
table 16.9. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
t
Indication
7.5 t
17.5 t
cyc
fails to meet the I
in high-speed mode and t
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
Standard mode
High-speed mode 300
Standard mode
High-speed mode 300
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
I
Specification
(Max.)
1000
1000
in standard mode fail to satisfy the I
2
C Bus
sr
) Values
Sr
/t
Sf
. Possible solutions that should be investigated
5 MHz
1000
300
100
300
Section 16 I
=
Rev. 3.00 Mar 21, 2006 page 477 of 788
Time Indication
8 MHz
937
300
1000
300
2
=
C bus interface specifications may
2
C Bus Interface (IIC) (Optional)
10 MHz
750
300
1000
300
2
C bus.
=
2
[ns]
C bus interface
2
C bus.
REJ09B0300-0300
16 MHz
468
300
1000
300
=
cyc
, as shown in
20 MHz
375
300
875
300
=