DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 26

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

6.6
6.7
6.8
Section 7 Data Transfer Controller (DTC)
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Rev. 3.00 Mar 21, 2006 page xxiv of liv
6.5.3
6.5.4
Burst ROM Interface......................................................................................................... 141
6.6.1
6.6.2
Idle Cycle .......................................................................................................................... 142
Bus Arbitration.................................................................................................................. 144
6.8.1
6.8.2
Features ............................................................................................................................. 145
Register Descriptions ........................................................................................................ 147
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Activation Sources ............................................................................................................ 152
Location of Register Information and DTC Vector Table ................................................ 153
Operation .......................................................................................................................... 155
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
Procedures for Using DTC................................................................................................ 163
7.6.1
7.6.2
Examples of Use of DTC .................................................................................................. 164
7.7.1
7.7.2
Usage Notes ...................................................................................................................... 166
7.8.1
7.8.2
7.8.3
Basic Operation Timing ....................................................................................... 131
Wait Control ........................................................................................................ 139
Basic Operation Timing ....................................................................................... 141
Wait Control ........................................................................................................ 142
Priority of Bus Masters ........................................................................................ 144
Bus Transfer Timing ............................................................................................ 144
DTC Mode Register A (MRA) ............................................................................ 147
DTC Mode Register B (MRB)............................................................................. 149
DTC Source Address Register (SAR).................................................................. 149
DTC Destination Address Register (DAR).......................................................... 149
DTC Transfer Count Register A (CRA) .............................................................. 150
DTC Transfer Count Register B (CRB)............................................................... 150
DTC Enable Registers (DTCER) ......................................................................... 150
DTC Vector Register (DTVECR)........................................................................ 151
Normal Mode....................................................................................................... 156
Repeat Mode ........................................................................................................ 157
Block Transfer Mode ........................................................................................... 158
Chain Transfer ..................................................................................................... 159
Interrupts.............................................................................................................. 160
Operation Timing................................................................................................. 160
Number of DTC Execution States........................................................................ 161
Activation by Interrupt......................................................................................... 163
Activation by Software ........................................................................................ 163
Normal Mode....................................................................................................... 164
Software Activation ............................................................................................. 165
Module Stop Mode Setting .................................................................................. 166
On-Chip RAM ..................................................................................................... 166
DTCE Bit Setting................................................................................................. 166
................................................................... 145