DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 482
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 482 of 847
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Section 16 I
Bit Bit Name
2
0
Rev. 3.00 Mar 21, 2006 page 426 of 788
REJ09B0300-0300
BBSY
SCP
2
C Bus Interface (IIC) (Optional)
Initial Value R/W
0
1
R/W
W
Description
Bus Busy
Start Condition/Stop Condition Prohibit
In master mode:
In slave mode:
[BBSY setting condition]
When the SDA level changes from high to low under the
condition of SCL = high, assuming that the start condition
has been issued.
[BBSY clearing condition]
When the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued.
To issue a start/stop condition, use the MOV instruction.
The I
before the issue of a start condition. Set MST to 1 and TRS
to 1 before writing 1 in BBSY and 0 in SCP.
The BBSY flag can be read to check whether the I
(SCL, SDA) is busy or free.
The SCP bit is always read as 1. If 0 is written, the data is
not stored.
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
Writing 1 in BBSY and 0 in SCP: A start condition and a
restart condition are issued
Writing to the BBSY flag is disabled.
2
C bus interface must be set in master transmit mode
2
C bus
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