DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 48

• Manufacturer Part Number: DF2161BVTE10
• Description: MCU 3V 128K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2161BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2161BVTE10; HD64F2161BVTE10

Figure 24.5
Figure 24.6
Figure 24.7
Figure 24.8
Figure 24.9
Section 25 Power-Down Modes
Figure 25.1
Figure 25.2
Figure 25.3
Figure 25.4
Section 27 Electrical Characteristics
Figure 27.1
Figure 27.2
Figure 27.3
Figure 27.4
Figure 27.5
Figure 27.6
Figure 27.7
Figure 27.8
Figure 27.9
Figure 27.10 Interrupt Input Timing ......................................................................................... 764
Figure 27.11 Basic Bus Timing (Two-State Access) ................................................................ 765
Figure 27.12 Basic Bus Timing (Three-State Access) .............................................................. 766
Figure 27.13 Basic Bus Timing (Three-State Access with One Wait State) ............................. 767
Figure 27.14 Burst ROM Access Timing (Two-State Access) ................................................. 768
Figure 27.15 Burst ROM Access Timing (One-State Access) .................................................. 769
Figure 27.16 I/O Port Input/Output Timing .............................................................................. 770
Figure 27.17 FRT Input/Output Timing.................................................................................... 770
Figure 27.18 FRT Clock Input Timing ..................................................................................... 771
Figure 27.19 8-Bit Timer Output Timing.................................................................................. 771
Figure 27.20 8-Bit Timer Clock Input Timing.......................................................................... 771
Figure 27.21 8-Bit Timer Reset Input Timing........................................................................... 771
Figure 27.22 PWM, PWMX Output Timing............................................................................. 772
Figure 27.23 SCK Clock Input Timing ..................................................................................... 772
Figure 27.24 SCI Input/Output Timing (Synchronous Mode) .................................................. 772
Figure 27.25 A/D Converter External Trigger Input Timing .................................................... 772
Figure 27.26 WDT Output Timing (RESO).............................................................................. 773
Figure 27.27 Host Interface (XBS) Timing............................................................................... 773
Figure 27.28 Keyboard Buffer Controller Timing .................................................................... 774
Rev. 3.00 Mar 21, 2006 page xlvi of liv
External Clock Input Timing ............................................................................... 636
Timing of External Clock Output Stabilization Delay Time ............................... 637
Subclock Input Timing ........................................................................................ 638
Processing for X1 and X2 Pins ............................................................................ 640
Note on Board Design of Oscillator Circuit Section............................................ 640
Mode Transition Diagram.................................................................................... 647
Medium-Speed Mode Timing.............................................................................. 650
Application Example in Software Standby Mode................................................ 652
Hardware Standby Mode Timing......................................................................... 653
Darlington Pair Drive Circuit (Example)............................................................. 708
LED Drive Circuit (Example).............................................................................. 709
Output Load Circuit ............................................................................................. 710
Connection of VCL Capacitor ............................................................................. 724
Connection of VCL Capacitor ............................................................................. 761
System Clock Timing .......................................................................................... 762
Oscillation Settling Timing.................................................................................. 762
Oscillation Setting Timing (Exiting Software Standby Mode) ............................ 763
Reset Input Timing .............................................................................................. 764