DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 258
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2367VF33V
Manufacturer:
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Section 6 Bus Controller (BSC)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
Rev.6.00 Mar. 18, 2009 Page 198 of 980
REJ09B0050-0600
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.51 and 6.52 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.
UCAS, LCAS
Address bus
Data bus
HWR
Figure 6.50 Example of Idle Cycle Operation in RAS Down Mode
RAS
RD
φ
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
T
p
DRAM space read
T
r
T
c1
T
c2
T
1
External read
T
2
T
3
Idle cycle
DRAM space write
T
i
T
c1
T
c2
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