DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 679

IC H8S/2367 MCU FLASH 128QFP

DF2367VF33V

Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2367VF33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.9
14.9.1
Table 14.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC
or DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data
transfer is performed by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DTC or DMAC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
SCI Interrupts
Interrupts in Normal Serial Communication Interface Mode
Section 14 Serial Communication Interface (SCI, IrDA)
Rev.6.00 Mar. 18, 2009 Page 619 of 980
REJ09B0050-0600

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