DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 264
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.8.2
Table 6.8 shows the pin states in an idle cycle.
Table 6.8
Pins
A23 to A0
D15 to D0
CSn (n = 7 to 0)
UCAS, LCAS
AS
RD
OE
HWR, LWR
DACKn (n = 1, 0)
Notes: 1. Remains low in DRAM space RAS down mode.
6.9
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.55 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
Rev.6.00 Mar. 18, 2009 Page 204 of 980
REJ09B0050-0600
2.
Pin States in Idle Cycle
Write Data Buffer Function
Remains low in a DRAM space refresh cycle.
Pin States in Idle Cycle
Pin State
Contents of following bus cycle
High impedance
High *
High *
High
High
High
High
High
1
2
*
2
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