DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 701
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
DF2367VF33V
Manufacturer:
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Quantity:
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Manufacturer:
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Bit Bit Name
1
0
15.3.6
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit Bit Name
7 to
1
0
AAS
ADZ
SVA6 to
SVA0
⎯
Slave Address Register (SAR)
Initial Value R/W
0
0
Initial Value R/W
0
0
R/W
R/W
R/W
R/W
Description
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
[Setting conditions]
•
•
[Clearing condition]
When 0 is written in AAS after reading AAS=1
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
When the general call address is detected in slave receive
mode
[Clearing conditions]
When 0 is written in ADZ after reading ADZ=1
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
Reserved
Though this bit can be read from or written to, the write
value should always be 0.
When the slave address is detected in slave receive
mode
When the general call address is detected in slave
receive mode.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 641 of 980
2
C bus.
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600
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