DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 368

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
Table 8.3
CHNE
0
0
0
1
1
1
1
8.5.1
In normal mode, one operation transfers one byte or one word of data. Table 8.4 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 8.4
Name
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Rev.6.00 Mar. 18, 2009 Page 308 of 980
REJ09B0050-0600
CHNS
—
—
—
0
1
1
1
Normal Mode
1st Transfer
Chain Transfer Conditions
Register Function in Normal Mode
DISEL
0
0
1
—
0
—
1
CR
Not 0
0
—
—
Not 0
0
Not 0
CHNE
—
0
0
0
0
DAR
CRA
—
—
0
—
0
—
Abbreviation
SAR
CRB
CHNS
—
—
—
—
—
—
—
—
—
—
—
2nd Transfer
DISEL
—
—
—
0
0
1
0
0
1
—
—
Designates destination address
Designates transfer count
Function
Designates source address
Not used
CR
—
—
—
Not 0
0
—
—
Not 0
0
—
—
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU