DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 730

• Manufacturer Part Number: DF2367VF33V
• Description: IC H8S/2367 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 A/D Converter
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps [2] and [3] are repeated as long as the
16.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in tables 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. The values given
in table 16.4 apply to the second and subsequent conversions.
Rev.6.00 Mar. 18, 2009 Page 670 of 980
REJ09B0050-0600
SPL
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
). The length of t
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total
D
) passes after the ADST bit is set to 1, then starts
CONV
) includes t
D
and the input sampling time