HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 114

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

4.5.3
94
NMI
IRL interrupts
On-chip module interrupts
Conditions: NMI pin edge detection
Operations: The PC and SR after the instruction that receives the interrupt are saved to the
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3–IRL0 level
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at
Conditions: The value of the interrupt mask bits in SR is lower than the on-chip module
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at
SPC and SSR, respectively. H'01C0 is set in INTEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by
SR.IMASK and is accepted with top priority when the BL bit in SR is 0. When the BL bit
is 1, the interrupt is masked. See section 6, Interrupt Controller, for more information.
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3–IRL0 level is set in INTEVT. The corresponding code is given as H'200 +
B'(IRL3–IRL0)
VBR + H'0600. The received level is not set in SR.IMASK. See section 6, Interrupt
Controller, for more information.
(TMU, RTC, SCI, CPG, REF) interrupt level and the BL bit in SR is 0. The interrupt is
accepted at an instruction boundary.
the time the interrupt is accepted is saved to SSR. The code corresponding to the interrupt
source is set in INTEVT. See table 6.4, Interrupt Exception Vectors and Rankings, for the
corresponding codes. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to
VBR + H'0600. B'0000 to B'1111 are set in the interrupt priority level registers (IRPA,
IRPB) within the interrupt controller. See section 6, Interrupt Controller, for more
information.
Interrupts
H'20. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to