HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 20

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Appendix A Pin Functions
A.1
A.2
A.3
A.4
Appendix B Control Registers
B.1
B.2
B.3
Appendix C Delay Time Variation Due to Load Capacitance
Appendix D Package Dimensions
x
17.3.4 Basic Timing ........................................................................................................ 512
17.3.5 Burst ROM Timing .............................................................................................. 515
17.3.6 DRAM Timing ..................................................................................................... 518
17.3.7 Synchronous DRAM Timing................................................................................ 528
17.3.8 Pseudo-SRAM Timing ......................................................................................... 539
17.3.9 PCMCIA Timing.................................................................................................. 544
17.3.10 Peripheral Module Signal Timing ........................................................................ 551
17.3.11 AC Characteristics Test Conditions ..................................................................... 554
Pin States ........................................................................................................................... 555
Pin Specifications .............................................................................................................. 558
Handling of Unused Pins ................................................................................................... 561
Pin States in Access to Each Address Space ..................................................................... 562
Register Address Map........................................................................................................ 598
Register Bit List................................................................................................................. 602
Register States in Reset and Power-Down States.............................................................. 608
................................................................................................ 555
......................................................................................... 598
................................................................................... 613
............................... 612