HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 318

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

In the case of consecutive word and byte accesses, or consecutive longword and byte accesses, in
area 6, CE1B and CE2B are asserted simultaneously in the byte access. As a result, a byte write
becomes a word-size write. In a byte read, the byte data at the specified address is read correctly.
Use one of the following methods to avoid this problem.
1. Do not use area 6 PCMCIA.
2. Use an 8-bit bus width for area 6 PCMCIA.
3. If a 16-bit bus width is used for area 6 PCMCIA, do not perform byte-size write accesses.
4. In consecutive accesses a. and b. below
10.4.3
1. Note the following concerning the SH7708 (not including the SH7708S and SH7708R).
2. Note the following concerning the SH7708 Series (SH7708, SH7708S, SH7708R).
298
a. Word access
b. Longword access
in which this problem arises, the problem can be avoided by performing a dummy read in a
non-cacheable area as shown in (a') and (b') below.
a'. Word access
b'. Longword access
When DRAM is connected in both area 2 and area 3, if
self-refreshing is executed for the memory in only one of the areas, or
a value corresponding to the above condition is written to the MCR or DCR register as a
program operation
after setting execution of CBR refreshing for both areas, use the procedure shown in (a), (b),
and (c) below.
a. Make a setting so that refreshing is not performed for either area 2 or area 3 (clear the
b. Execute self-refreshing for one of the areas.
c. Make a new setting so that auto-refreshing is executed for the area in which self-refreshing
If the refresh mode bit (the RMODE bit in registers MCR and DCR) is to be changed while the
a. Clear the refresh control bit to 0.
b. When refreshing is not being performed, set the refresh control bit to 1 again and then
RFSH bit to 0 in both the MCR and DCR registers).
is not used.
refresh control bit (the RFSH bit in registers MCR and DCR) is set to 1, use the procedure
shown in a. and b. below.
change the refresh mode.
Self-Refreshing
byte access (write)
dummy read
byte access (write)
dummy read
byte access (write)
byte access (write)