HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 117

IC SUPERH MPU ROMLESS 144LQFP

HD6417708SF60

Manufacturer Part Number
HD6417708SF60
Description
IC SUPERH MPU ROMLESS 144LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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5.1
5.1.1
The cache specifications are listed in table 5.1.
Table 5.1
Parameter
Capacity
Structure
Line size
Number of entries
Write system
Replacement method
5.1.2
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 128 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes
entries), with a total of 8 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache
structure.
Overview
Features
Cache Structure
Cache Specifications
Specification
Selectable:
Instruction/data mixed, 4-way set associative (2-way set associative in
RAM mode)
16 bytes
128 entries/way
P0, P1, P3, U0: Write-back/write-through selectable
Least-recently-used (LRU) algorithm
Section 5 Cache
Normal mode: 8 kbytes
RAM mode: 4 kbytes cache and 4 kbytes RAM
4). The data capacity per way is 2 kbytes (16 bytes 128
97

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