HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 165

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

8.3
8.3.1
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting
modules continue to run during sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low. However, during a
refresh cycle, the STATUS1 pin and STATUS0 pin are both set low.
8.3.2
Sleep mode is canceled by an interrupt (NMI, IRL, on-chip supporting module) or reset. Interrupts
are accepted during sleep mode even when the BL bit in the SR register is 1.
Canceling with an Interrupt: When an NMI, IRL or on-chip supporting module interrupt occurs,
sleep mode is canceled and interrupt exception handling is executed. A code indicating the
interrupt source is set in the INTEVT register.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
8.4
8.4.1
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The
chip moves from the program execution state to standby mode. In standby mode, power
consumption is greatly reduced by halting not only the CPU, but the clock and on-chip supporting
modules as well. The clock output from the CKIO pin also halts. CPU and cache register contents
are held, but some on-chip supporting modules are initialized. Table 8.4 lists the states of registers
in standby mode.
Sleep Mode
Transition to Sleep Mode
Canceling Sleep Mode
Standby Mode
Transition to Standby Mode
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