HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 298

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Refreshing: The bus state controller includes a function for controlling pseudo-SRAM refreshing.
Distributed refreshing by means of auto-refresh cycles can be performed by clearing the RMODE
bit to 0 and setting the RFSH bit to 1 in MCR.
Refreshing is performed at intervals determined by the input clock selected by bits CKS2–CKS0
in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set
so as to satisfy the refresh interval stipulation for the pseudo-SRAM used. First set the RTCOR,
RTCNT, and the RMODE and RFSH bits in MCR, then set the CKS2–CKS0. When the clock is
selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT
value is constantly compared with the RTCOR value, and if the two values are the same, a refresh
request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero
and the count-up is restarted. Figure 10.37 shows the auto-refresh cycle timing.
The number of OE assert cycles for auto-refreshing is specified by the TRAS bits in MCR. The
precharge time from OE negation until the next assertion of CE is determined by the setting of the
TPC bits in MCR.
Auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset.
278
CKIO
CE
OE/RFSH
Figure 10.37 Pseudo-SRAM Auto-Refreshing
TRc
TRr1
TRr2
(Tpc)