HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 238

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

H'FFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to
the SDMR register. When H'0230 is written to the SDMR register of area 3, random data is
written to the address H'FFFE000 (address Y) + H'08C0 (value X) or H'FFFFE8C0. As a result,
H'0230 is written to the SDMR register. The range for value X is H'000 to H'0FFC.
Note: Depending on the type of synchronous DRAM.
10.2.9
The refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. RTSCR is initialized
to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Note: The method for writing to RTCOR is different from that for general registers to prevent
Bits 15 to 8—Reserved: These bits always read 0.
218
Initial value:
Initial value:
Initial value:
Initial value:
inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper
byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on
Accessing Refresh Control Related Registers.
Bit name:
Bit name:
Bit name:
Bit name:
Refresh Timer Control/Status Register (RTCSR)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Address bits
CMF
R/W
31
—
—
—
15
—
W
7
0
R
7
0
SDMR address
· · · · · · · · · · · · ·
· · · · · · · · · · · · ·
CMIE
R/W
—
14
—
W
6
0
R
6
0
CKS2
R/W
—
13
—
W
5
0
R
5
0
CKS1
R/W
12
—
—
—
12
—
W
4
0
R
4
0
CKS0
R/W
W*
11
—
—
11
—
W
3
0
R
3
0
OVF
R/W
W*
10
—
—
10
—
W
2
0
R
2
0
OVIE
R/W
—
—
—
—
W
9
1
9
0
R
1
0
LMTS
R/W
—
—
—
—
W
8
0
8
0
R
0
0