HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 135

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

6.3
6.3.1
Interrupt priority registers A and B (IPRA and IPRB) are 16-bit read/write registers that set
priority levels from 0 to 15 for on-chip supporting module interrupts. These registers are
initialized to H'0000 by a reset. They are not initialized in standby mode.
Table 6.5 lists the relationship between the interrupt sources and the IPRA and IPRB bits.
Table 6.5
Register
IPRA
IPRB
Notes: 1. REF is the memory refresh unit in the bus state controller. See section 10, Bus State
As listed in table 6.5, four sets of on-chip supporting modules are assigned to each register. 4-bit
groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000)
to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15
(the highest level).
Initial value:
Initial value:
2. Reserved bits: Always read 0. Only 0 should be written.
Bit name:
Bit name:
INTC Registers
Interrupt Priority Registers A and B (IPRA, IPRB)
Controller, for details.
Interrupt Request Sources and IPRA, IPRB
R/W:
R/W:
Bit:
Bit:
Bits 15 to 12
TMU0
WDT
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Bits 11 to 8
TMU1
REF*
R/W
R/W
13
0
5
0
1
R/W
R/W
12
0
4
0
Bits 7 to 4
TMU2
SCI
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
Bits 3 to 0
RTC
Reserved *
R/W
R/W
9
0
1
0
2
R/W
R/W
8
0
0
0
115