HD6417708SF60 Renesas Electronics America, HD6417708SF60 Datasheet - Page 141

• Manufacturer Part Number: HD6417708SF60
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 6.6
Item
Response
time
Icyc:
Bcyc: Duration of one CKIO cycle
Pcyc: Duration of one cycle of peripheral clock supplied to supporting modules
Notes: 1. S also includes the memory access wait time.
Duration of one cycle of internal clock supplied to CPU, etc.
2. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1.
3. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1/4.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires 7 instruction execution cycles. When
external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
Total
Minimum
case*
Maximum
case*
Interrupt Response Time (cont)
2
3
NMI
(5.5 + X)
+ 0.5
+ 0.5
6.5
7 + S
Bcyc
Pcyc
Icyc
Number of States
RL
(5.5 + X)
+ 0.5
+ 2
8
13 + S
Pcyc
Bcyc
Icyc
Peripheral
Modules
(5.5 + X)
+ 1.5
7
10.5 + S
Pcyc
Icyc
Notes
At 60 MHz operation:
0.10–0.14 µs
At 60 MHz operation:
0.23–0.34 µs (in case of
operand cache-hit)
At 60 MHz operation:
0.27–0.37 µs (when
external memory access
is performed with wait =
0)
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